Design of universal logic gates using homo and hetero-junction double gate TFETs with pseudo-derived logic

This work explores homo- and heterojunction tunnel field-effect transistor (TFET)-based NAND NOR logic circuits using 30 nm technology compares their performance in terms of power consumption propagation delay. By implementing homojunction TFET-based circuits, it has been observed that consumes less than the gate since current drawn by PTFET pull-up network is higher. The delay lower due to its reduced internal capacitances. To meet enhanced both shorted independent double-gate (GaSb-InAs) TFETs are designed implemented. In order reduce further, pseudo-derived implemented for first time. Heterojunction with circuit shows a 103 times reduction 0.75 compared circuit.